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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2009-2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. single, dual, quad general purpose micropower, rrio operational amplifier isl28113, isl28213, isl28413 the isl28113, isl28213, and isl28413 are single, dual, and quad channel general purpose micropower, rail-to-rail input and output operational amplifiers wi th supply voltage range of 1.8v to 5.5v. key features are a low supply current of 130a maximum per channel at room temperature, a low bias current and a wide input voltage range, which enables the isl28x13 devices to be excellent general purpose op-amps for a wide range of applications. the isl28113 is available in the sc70-5 and sot23-5 packages, the isl28213 is in the msop8, soic8, sot23-8 packages, and the isl28413 is in the tssop14, soic14 packages. all devices operate over the extended temperature range of -40c to +125c. related literature ?see an1519 for ?isl28213/14soiceval2z evaluation board user?s guide? ?see an1520 for ?isl28113/14sot23eval1z evaluation board user?s guide? ?see an1542 for ?isl28213/14msopeval2z evaluation board user?s guide? features ? low current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 130a ? wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v ? gain bandwidth product . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mhz ? input bias current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20pa, max. ? operating temperature range. . . . . . . . . . . . .-40c to +125c ?packages - isl28113 (single) . . . . . . . . . . . . . . . . . . . . . sc70-5, sot23-5 - isl28213 (dual). . . . . . . . . . . . . . . . msop8, soic8, sot23-8 - isl28413 (quad) . . . . . . . . . . . . . . . . . . . . . soic14, tssop14 applications ? power supply control/regulation ? process control ? signal gain/buffers ? active filters ? current shunt sensing ?trans-impedance amps in- in+ rf rref+ isl28x13 +5v v- v+ rin- 10k ? rin+ 10k ? - + 100k ? vref 100k ? vout load rsense single-supply, low-side current sense amplifier gain = 10 figure 1. typical application june 9, 2011 fn6728.5
isl28113, isl28213, isl28413 2 fn6728.5 june 9, 2011 ordering information part number (notes 2, 3) part marking package (pb-free) pkg. dwg. # isl28113fez-t7 (note 1) bja 5 ld sc-70 p5.049 isl28113fez-t7a (note 1) bja 5 ld sc-70 p5.049 isl28113fhz-t7 (note 1) bcya 5 ld sot-23 p5.064a isl28113fhz-t7a (note 1) bcya 5 ld sot-23 p5.064a isl28213fuz 8213z 8 ld msop m8.118a isl28213fuz-t7 (note 1) 8213z 8 ld msop m8.118a isl28213fbz 28213 fbz 8 ld soic m8.15e isl28213fbz-t7 (note 1) 28213 fbz 8 ld soic m8.15e isl28213fbz-t13 (note 1) 28213 fbz 8 ld soic m8.15e coming soon isl28213fhz-t7 (note 1) tbd 8 ld sot-23 p8.064 coming soon isl28213fhz-t7a (note 1) tbd 8 ld sot-23 p8.064 isl28413fvz 28413 fvz 14 ld tssop mdp0044 isl28413fvz-t7 (note 1) 28413 fvz 14 ld tssop mdp0044 ISL28413FVZ-T13 (note 1) 28413 fvz 14 ld tssop mdp0044 isl28413fbz 28413 fbz 14 ld soic mdp0027 isl28413fbz-t7 (note 1) 28413 fbz 14 ld soic mdp0027 isl28413fbz-t13 (note 1) 28413 fbz 14 ld soic mdp0027 isl28113sot23eval1z evaluation board isl28213msopeval2z evaluation board isl28213soiceval2z evaluation board coming soon isl28413tssopeval1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl28113 , isl28213 , isl28413 . for more information on msl please see techbrief tb363 . pin configurations isl28113 (5 ld sc-70) top view isl28113 (5 ld sot-23) top view isl28213 (8 ld msop, 8 ld soic, 8 ld sot-23) top view in+ v s - in- v s + out 1 2 3 5 4 out v s - in+ v s + in- 1 2 3 5 4 out_a in-_a in+_a v s - v s + out_b in-_b in+_b 1 2 3 45 6 7 8
isl28113, isl28213, isl28413 3 fn6728.5 june 9, 2011 isl28413 (14 ld tssop, 14 ld soic) top view pin configurations (continued) out_a in-_a in+_a v s + in+_b in-_b out_b out_d in-_d in+_d v s - in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 pin descriptions pin name pin number description 5 ld sc-70 5 ld sot-23 8 ld msop, 8ld soic, 8ldsot-23 14 ld tssop, 14 ld soic out out_a out_b out_c out_d 41 1 7 1 7 8 14 output circuit 1 v s - 2 2 4 11 negative supply voltage circuit 2 in+ in+_a in+_b in+_c in+_d 13 3 5 3 5 10 12 positive input circuit 3 in- in-_a in-_b in-_c in-_d 34 2 6 2 6 9 13 negative input v s + 5 5 8 4 positive supply voltage see ?circuit 2? v + v- out v+ v- capacitively triggered esd clamp in+ in- v+ v-
isl28113, isl28213, isl28413 4 fn6728.5 june 9, 2011 absolute maximum ratings (t a = +25c) thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5v supply turn-on voltage slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1v/s differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma differential input voltage . . . . . . . . . . . . . . . . . . . . . . .v - - 0.5v to v + + 0.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v - - 0.5v to v + + 0.5v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000v machine model isl28113, isl28213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350v isl28413. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000v thermal resistance (typical) ja (c/w) jc (c/w) 5 ld sc-70 (notes 4, 5) . . . . . . . . . . . . . . . . 250 n/a 5 ld sot-23 (notes 4, 5) . . . . . . . . . . . . . . . 225 n/a 8 ld msop (notes 4, 5) . . . . . . . . . . . . . . . . 180 100 8 ld soic package (notes 4, 5) . . . . . . . . . 126 90 8 ld sot-23 (notes 4, tbd) . . . . . . . . . . . . 240 tbd 14 ld tssop package (notes 4, 5) . . . . . . 120 40 14 ld soic package (notes 4, 5). . . . . . . . 90 50 ambient operating temperature range . . . . . . . . . . . . . . -40c to +125c storage temperature range . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 5. for jc , the ?case temp? location is the top of the package. electrical specifications v s + = 5v, v s - = 0v, r l = open, v cm = v s /2, t a = +25c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c , unless otherwise specified. parameter description conditions min (note 6) typ max (note 6) unit dc specifications v os input offset voltage -5 0.5 5 mv -6 6 mv tcv os input offset voltage temperature coefficient -40c to +125c 2 10 v/c i os input offset current 130 pa i b input bias current isl28113 -20 3 20 pa -100 100 pa isl28213, isl28413 -20 3 20 pa -50 50 pa common mode input voltage range - 0.1v +5.1v v z in input impedance 10 12 ? c in input capacitance 1 pf cmrr common mode rejection ratio vcm = -0.1v to 5.1v 72 db -40c to +125c 70 db psrr power supply rejection ratio v s = 1.8v to 5.5v 71 db -40c to +125c 70 db v oh output voltage swing, high r l = 10k ? 4.985 4.993 v 4.98 v v ol output voltage swing, low r l = 10k ? 13 15 mv 20 mv v + supply voltage 1.8 5.5 v
isl28113, isl28213, isl28413 5 fn6728.5 june 9, 2011 i s supply current per amplifier r l = open 90 130 a 170 a i sc+ output source short circuit current r l = 10 ? to v- -22 ma i sc- output sink short circuit current r l = 10 ? to v+ 16 ma ac specifications gbwp gain bandwidth product v s = 2.5v a v = 100, r f = 100k ? , r g =1k ? , r l = 10k ? to v cm 2mhz e n v p-p peak-to-peak input noise voltage v s = 2.5v f = 0.1hz to 10hz 14 v p-p e n input noise voltage density v s = 2.5v f = 1khz 55 nv/ (hz) i n input noise current density v s = 2.5v f = 1khz 5fa/ (hz) c in differential input capacitance v s = 2.5v f = 1mhz 1.0 pf common mode input capacitance 1.3 pf transient response sr slew rate 20% to 80% v out v out = 0.5v to 4.5v 1 v/s t r , t f , small signal rise time, t r 10% to 90% v s = 2.5v a v = +1, v out = 0.05v p-p , r f =0 ? , r l = 10k ? , c l = 15pf 100 ns fall time, t f 10% to 90% 115 ns t s settling time to 0.1%, 4v p-p step v s = 2.5v a v = +1, r f = 0 ? , r l =10k ? , c l = 1.2pf 7.5 s note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications v s + = 5v, v s - = 0v, r l = open, v cm = v s /2, t a = +25c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c , unless otherwise specified. (continued) parameter description conditions min (note 6) typ max (note 6) unit
isl28113, isl28213, isl28413 6 fn6728.5 june 9, 2011 typical performance curves v s = 2.5v, v cm = 0v, r l = open, unless otherwise specified. figure 2. input bias current vs temperature figure 3. input noise voltage spectral density figure 4. open-loop gain, phase vs frequency, r l = 100k , c l = 10pf, v s = 0.9v figure 5. open-loop gain , phase vs frequency, r l =100k , c l = 10pf, v s = 2.5v figure 6. cmrr vs frequency, v s = 2.5 figure 7. psrr vs frequency, v s = 0.9v, 2.5v -50 -40 -30 -20 -10 0 10 20 30 40 50 -40 -20 0 20 40 60 80 100 120 140 temperature (c) i bias (pa) simulation frequency (hz) 10 100 1000 input noise voltage (nv/ hz) 1 10 100 1k 10k 100k v + = 2.5v a v = 1 10,000 -80 -60 -40 -20 0 20 40 60 80 100 120 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open loop gain (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 phase () r l = 100k simulation c l = 10pf phase gain v + = 0.9v -80 -60 -40 -20 0 20 40 60 80 100 120 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open loop gain (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 phase () r l = 100k simulation c l = 10pf phase gain v + = 2.5v 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) cmrr (db) simulation psrr (db ) frequency (hz) 0 10 20 30 40 50 60 70 80 100 1k 10k 100k 1m 10m r l = inf a v = +1 v cm = 100mv p-p c l = 4pf psrr- v s = 2.5v psrr+ v s = 0.9v psrr- v s = 0.9v psrr+ v s = 2.5v
isl28113, isl28213, isl28413 7 fn6728.5 june 9, 2011 figure 8. frequency response vs closed loop gain figure 9. frequency response vs v out figure 10. gain vs frequency vs r l figure 11. gain vs frequency vs c l figure 12. gain vs frequency vs supply voltage figure 13. crosstalk, v s = 2.5v typical performance curves v s = 2.5v, v cm = 0v, r l = open, unless otherwise specified. (continued) frequency (hz) gain (db) 100k 1m 10m 10 10k 1k 100 70 -10 0 10 20 30 40 50 60 100m v + = 2.5v v out = 50mv p-p c l = 4pf r l = 10k a v = 1 a v = 100 a v = 1000 a v = 10 r g = 100, r f = 100k r g = open, r f = 0 r g = 1k, r f = 100k r g = 10k, r f = 100k normalized gain (db) frequency (hz) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 1k 10k 100k 1m 10m v s = 2.5v a v = +1 r l = 10k c l = 4pf v out = 1v p-p v out = 100mv p-p v out = 50mv p-p v out = 10mv p-p v out = 500mv p-p v out = 200mv p-p normalized gain (db) frequency (hz) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 1k 10k 100k 1m 10m v + = 2.5v a v = +1 v out = 50mv p-p c l = 4pf r l = 49.9k r l = 1k r l = 499 r l = 100 r l = 10k r l = 4.99k normalized gain (db) frequency (hz) 100k 1m 10m 10k 1k -4 -3 -2 -1 0 1 2 3 4 5 6 v s = 2.5v r l = 10k a v = +1 v out = 50mv p-p c l = 1004pf c l = 474pf c l = 224pf c l = 104pf c l = 26pf c l = 4pf normalized gain (db) frequency (hz) 100k 1m 10m 10k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 c l = 4pf r l = 10k a v = +1 v out = 50mv p-p v s = 2.5v v s = 0.9v v s = 1.25v v s = 1.75v 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m 10m cross-talk (db) frequency (hz) r l -receiver = 10k a v = +1 v source = 1v p-p c l = 4pf r l -driver = inf v s = 2.5v
isl28113, isl28213, isl28413 8 fn6728.5 june 9, 2011 figure 14. small signal transient response, v s = 2.5v figure 15. large signal transient response vs r l v s = 0.9v, 2.5v figure 16. negative output overload response time, v s = 0.9v, 2.5v figure 17. positive output overload response time, v s = 0.9v, 2.5v figure 18. % overshoot vs load capacitance, v s = 2.5v typical performance curves v s = 2.5v, v cm = 0v, r l = open, unless otherwise specified. (continued) time (ns) small signal (mv) -30 -20 -10 0 10 20 30 0 200 400 600 800 1000 1200 1400 1600 1800 2000 r l = 10k a v = +1 c l = 15pf v out = 50mv p-p v s = 2.5v -3 -2 -1 0 1 2 3 0 2 4 6 8 101214161820 time (ms) large signal (v) r l = 10k a v = +1 c l = 15pf v out = rail v s = 0.9v v s = 2.5v 012345678910 time (ms) input (v) output (v) -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 input r l = inf a v =10 c l = 15pf r f = 9.09k, r g = 1k output @ v s =0.9v output @ v s = 2.5v -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 012345678910 time (ms) input (v) -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 output (v) input r l = inf a v =10 c l = 15pf r f = 9.09k, r g = 1k output @ v s =0.9v output @ v s = 2.5v capacitance (pf) 10 100 1k 10k overshoot (%) 0 10 20 30 40 50 60 70 80 90 o v e r s h o o t + v s = 2.5v r l = 10k a v = 1 v out = 50mv p-p o v e r s h o o t -
isl28113, isl28213, isl28413 9 fn6728.5 june 9, 2011 applications information functional description the isl28113, isl28213 and isl28413 are single, dual and quad, cmos rail-to-rail input, output (rrio) micropower operational amplifiers. they are de signed to operate from single supply (1.8v to 5.5v) or dual supply (0.9v to 2.75v). the parts have an input common mode range that extends 100mv above and below the power supply voltage rails. the output stage can swing to within 15mv of the supply rails with a 10k load. input esd diode protection all input terminals have internal esd protection diodes to both positive and negative supply rail s, limiting the input voltage to within one diode beyond the supply rails (see ?pin descriptions - circuit 1? on page 3 ) . for applications where the input voltage may exceed either power supply voltage by 0.5v or more, an external series resistor must be used to ensure the input currents never exceed 20ma (see figure 19). output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the isl28113, isl28213 and isl28413 are immune to output phase reversal, even when the input voltage is 1v beyond the supplies. unused channels if the application requires less th an all amplifiers one channel, the user must configure the unused channel(s) to prevent it from oscillating. the unused channel(s) will oscillate if the input and output pins are floating. this will result in higher than expected supply currents and possible noise injection into the channel being used. the proper way to prevent this oscillation is to short the output to the inverting input and ground the positive input (as shown in figure 20). power dissipation it is possible to exceed the +125c maximum junction temperatures under certain load, power supply conditions and ambient temperature conditions. it is therefore important to calculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1: where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2: where: ?t max = maximum ambient temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent suppl y current of 1 amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance isl28113, isl28213 and isl28413 spice model figure 21 shows the spice model schematic and figure 22 shows the net list for the spice model. the model is a simplified version of the actual device and simulates important ac and dc parameters. ac parameters incorporated into the model are: 1/f and flatband noise, slew rate, cmrr, gain and phase. the dc parameters are ios, total supply current and output voltage swing. the model uses typical parameters given in the ?electrical specifications? table beginning on page 4. the avol is adjusted for 85db with the dominate pole at 100hz. the cmrr is set 72db, f = 35khz). the input stage models th e actual device to present an accurate ac representation. the model is configured for ambient temperature of +25c. figures 23 through 32 show the characterization vs simulation results for the noise voltage, closed loop gain vs frequency, large signal 5v step response , cmrr and open loop gain phase. figure 19. input esd diode current limiting - + r in - r l v in - v+ v- r in + r f r g figure 20. preventing oscillations in unused channels - + t jmax t max ja xpd maxtotal + = (eq. 1) pd max v s i qmax v s ( - v outmax ) v outmax r l ------------------------ + = (eq. 2)
isl28113, isl28213, isl28413 10 fn6728.5 june 9, 2011 license statement the information in this spice model is protected under the united states copyright laws. intersil corporation hereby grants users of this macro-model hereto referred to as ?licensee?, a nonexclusive, nontransferable licence to use this model as long as the licensee abides by the terms of this agreement. before using this macro-model, the licensee should read this license. if the licensee does not accept these terms, permission to use the model is not granted. the licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the licensee?s company. the licensee may modify the macro-model to suit his/her specific applications, and the licensee may make copies of this macro-model for use within their company only. this macro-model is provided ?as is, where is, and with no warranty of any kind either expressed or implied, including buy not limited to any implied warranties of merchantability and fitness for a particular purpose.? in no event will intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. intersil reserves the right to make changes to the product and th e macro-model without prior notice.
isl28113, isl28213, isl28413 11 fn6728.5 june 9, 2011 ios 25e-12 eos vcm + - + - g1a g2a 1 1 14 ra1 ra2 4 5 v++ d1 dx d2 dx r10 1e9 100 r9 15 r6 v2 1e-6v + - v1 1e-6v + - r5 r7 r8 10 10 1 1 i2 5e-3 6 i1 5e-3 r2 r1 r3 r4 1.0004 10 10 cin1 1.26pf cin2 1.26pf cindiff 1.02pf r22 5e11 r23 5e11 + - + - en v out v+ v- + - + - + - + - d3 dx d4 dx v3 0.61v v4 0.61v g1 g2 r11 1 r12 1 4 5 v++ 16 18 17 + - + - + - + - d5 dx d6 dx v5 v6 0.604v g3 g4 r13 r14 vg 20 19 c2 5.0nf c3 5.0nf vmid vmid + - + - g5 g6 r15 1e6 r16 22 21 l1 4.5474 l2 4.5474 1e6 vcm + - + - isy 90ua v++ v- v+ + - + - g11 g12 r19 50 r20 26 27 50 v-- vcm vc + - + - d11 dy d12 dy d9 dx d10 dx d7 dx d8 dx vg v++ v-- v-- + - + - v7 v8 0.08v 0.08v vg + - + - vc g10 g9 vout 24 25 1 st gain stage (cont) mid supply ref 2 nd gain stage common mode gain stage supply isolation stage e2 e3 output stage c4 10pf c3 10pf r17 5305.32 r18 5305.32 23 + - g8 + - g7 vmid vmid 0.604v 318.329e3 318.329e3 + - + - e4 pole stage + - + - vin+ + - en r21 800e3 v9 0.00035v d13 dn v-- v-- 28 29 in+ 1 2 3 4 5 vmid vc 11 12 9 10 13 7 8 1.0004 m14 m15 m16 m17 1 st gain stage input stage vin- vmid vc figure 21. spice schematic figure 21. spice schematic voltage noise stage
isl28113, isl28213, isl28413 12 fn6728.5 june 9, 2011 * source isl28113_spicemodel * revision d, lafontaine february 22, 2010 improved noise performance * model for noise, supply currents, cmrr 72db f=35khz, avol 85db f=100hz * sr = 1.0v/us, gbwp 2mhz, 2nd pole 3mhz output voltage clamp and short ckt i limit *copyright 2009 by intersil corporation *refer to data sheet ?license statement? use of *this model indicates your acceptance with the *terms and provisions in the license statement. * connections: +input * | -input * | | +vsupply * | | | -vsupply * | | | | output * | | | | | .subckt isl28113subckt vin+ vin- v+ v- vout * source isl28113_ds rev1 * *voltage noise e_en vin+ en 28 0 1 d_d13 29 28 dn v_v9 29 0 0.45 r_r21 28 0 30 * *input stage m_m14 3 1 5 5 nchannelmosfet m_m15 4 vin- 6 6 nchannelmosfet m_m16 11 vin- 9 9 pmosisil m_m17 12 1 10 10 pmosisil i_i1 7 v-- dc 5e-3 i_i2 v++ 8 dc 5e-3 i_ios vin- 1 dc 25e-12 g_g1a v++ 14 4 3 1404 g_g2a v-- 14 11 12 1404 v_v1 v++ 2 1e-6 v_v2 13 v-- 1e-6 r_r1 3 2 1.0004 r_r2 4 2 1.0004 r_r3 5 7 10 r_r4 7 6 10 r_r5 9 8 10 r_r6 8 10 10 r_r7 13 11 1 r_r8 13 12 1 r_ra1 14 v++ 1 r_ra2 v-- 14 1 c_cindif vin- en 1.02e-12 c_cin1 v-- en 1.26e-12 c_cin2 v-- vin- 1.26e-12 * *1st gain stage g_g1 v++ 16 15 vmid 334.753e-3 g_g2 v-- 16 15 vmid 334.753e-3 v_v3 17 16 .61 v_v4 16 18 .61 d_d1 15 vmid dx d_d2 vmid 15 dx d_d3 17 v++ dx d_d4 v-- 18 dx r_r9 15 14 100 r_r10 15 vmid 1e9 r_r11 16 v++ 1 r_r12 v-- 16 1 * *2nd gain stage g_g3 v++ vg 16 vmid 24.893e-3 g_g4 v-- vg 16 vmid 24.893e-3 v_v5 19 vg .604 v_v6 vg 20 .604 d_d5 19 v++ dx d_d6 v-- 20 dx r_r13 vg v++ 318.329e3 r_r14 v-- vg 318.329e3 c_c2 vg v++ 5e-09 c_c3 v-- vg 5e-09 * *mid supply ref e_e4 vmid v-- v++ v-- 0.5 e_e2 v++ 0 v+ 0 1 e_e3 v-- 0 v- 0 1 i_isy v+ v- dc 90e-6 * *common mode gain stage with zero g_g5 v++ vc vcm vmid 0.25118 g_g6 v-- vc vcm vmid 0.25118 e_eos 1 en vc vmid 1 r_r15 vc 21 0.001 r_r16 22 vc 0.001 r_r22 en vcm 5e11 r_r23 vcm vin- 5e11 l_l1 21 v++ 4.547418e-09 l_l2 22 v-- 4.547418e-09 * *pole stage g_g7 v++ 23 vg vmid 0.18849 g_g8 v-- 23 vg vmid 0.18849 r_r17 23 v++ 5.30532 r_r18 v-- 23 5.30532 c_c4 23 v++ 1e-8 c_c5 v-- 23 1e-8 * *output stage with correction current sources g_g9 26 v-- vout 23 0.02 g_g10 27 v-- 23 vout 0.02 g_g11 vout v++ v++ 23 0.02 g_g12 v-- vout 23 v-- 0.02 v_v7 24 vout .08 v_v8 vout 25 .08 d_d7 23 24 dx d_d8 25 23 dx d_d9 v++ 26 dx d_d10 v++ 27 dx d_d11 v-- 26 dy d_d12 v-- 27 dy r_r19 vout v++ 50 r_r20 v-- vout 50 .model pmosisil pmos (kp=16e-3 vto=-0.6) .model nchannelmosfet nmos (kp=3e-3 vto=0.6) .model dn d(kf=6.69e-9 af=1) .model dx d(is=1e-12 rs=0.1) .model dy d(is=1e-15 bv=50 rs=1) .ends isl28113subckt figure 22. spice net list
isl28113, isl28213, isl28413 13 fn6728.5 june 9, 2011 characterization vs simulation results figure 23. characterized input noise voltage figure 24. simulated input noise voltage figure 25. characterized closed loop gain vs frequency figure 26. simulated closed loop gain vs frequency figure 27. characterized large signal transient response vs r l , v s = 0.9v, 2.5v figure 28. simulated large sign al transient response vs r l , v s = 0.9v, 2.5v frequency (hz) 10 100 1000 input noise voltage (nv/ hz) 1 10 100 1k 10k 100k v + = 2.5v a v = 1 10,000 frequency (hz) 1 10 100 1k 10k 100k 10 100 1000 10,000 input noise voltage (nv/ hz) frequency (hz) gain (db) 100k 1m 10m 10 10k 1k 100 70 -10 0 10 20 30 40 50 60 100m v + = 2.5v v out = 50mv p-p c l = 4pf r l = 10k a v = 1 a v = 100 a v = 1000 a v = 10 r g = 100, r f = 100k r g = 10k, r f = 100k r g = 1k, r f = 100k r g = open, r f = 0 gain (db) (a) ac sims.dat (active) frequency (hz) 10 100 1.0k 10k 100k 1.0m 10m 100m 0 20 40 60 -10 70 -3 -2 -1 0 1 2 3 02468101214161820 time (ms) large signal (v) r l = 10k a v = +1 c l = 15pf v out = rail v s = 0.9v v s = 2.5v (a) ac sims.dat (active) time (s) 051015202530 -3 -2 -1 -0 1 2 3 r l = 10k a v = +10 c l = 15pf v out = rail v s = 2.5v v out v in large signal (v)
isl28113, isl28213, isl28413 14 fn6728.5 june 9, 2011 figure 29. simulated (design) open-loop gain, phase vs frequency figure 30. simulated (spice) open-loop gain, phase vs frequency figure 31. simulated (design) cmrr figure 32. simulated (spice) cmrr characterization vs simulation results (continued) -80 -60 -40 -20 0 20 40 60 80 100 120 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open loop gain (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 phase () r l = 100k simulation c l = 10pf phase gain v + = 2.5v open loop gain (db)/phase () (a) ac sims.dat (active) frequency (hz) 0.01 0.1 10 100 1.0k 10k 100k 1.0m 10m 100m 0 40 80 120 160 200 1.0 0 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) cmrr (db) simulation cmrr (db ) (a) ac sims.dat (active) frequency (hz) 0.01 0.1 1.0 1.0k 10k 100k 10m 0 20 40 60 80 100 1.0m 100m 10
isl28113, isl28213, isl28413 15 fn6728.5 june 9, 2011 revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/18/11 fn6728.5 - on page 2, ordering information table: isl28113 fhz-t7 & -t7a pkg dwg # changed from mdp0038 (obsoleted) to p5.064a. removed isl28213fhz and added ?coming soon? to parts isl28213fhz-t7a and isl28413tssopeval1z. - on page 3, pin descriptions: circui t 3 diagram, removed anti-parallel diodes from the in+ to in- terminals. - on page 4, absolute maximum ratings: changed differential input voltage from "0.5v" to "v - - 0.5v to v + + 0.5v". - on page 4, updated cmrr and psrr parameters in electrical specifications table with test condition specifiying -40c to 125c typical parameter. - on page 5, updated note 6 (?over-temp? note) referenced in min and max column headings of electrical specifications table from "parameters with min and/or max limits are 1 00% tested at +25c, unless otherwise specified. temperature limits established by characterization an d are not production tested." to new standard "compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." - on page 9, under ?input esd diode protection,? removed ?they also contain back to-b ack diodes across the input terminals.? changed ?for applications where the input differenti al voltage is expected to exceed 0.5v, an external series resistor...? to ?for applications where the input differential voltage may exceed either power supply voltage by 0.5v or more, an external series resistor...?. removed ?although the ampl ifier is fully protected, high input slew rates that exceed the amplifier slew rate (1v/s) may cause output distortion.? - on page 9, figure 19: updated circuit schematic by removing back-to-back input protection diodes. - on page 18, replaced package outline drawing mdp0038 (obsolete) with p5.064a. 3/23/10 fn6728.4 page 1, 2nd paragraph - added ?...sot23-8 packages...? and changed ?so8? to ?soic8?. also global, changed s08 to soic8 pg 2, ordering information table: part # isl28213fez changed to isl28213fhz and part marking changed to "tbd" -added related literature on page 1, updated ordering information by adding eval boards. -added to ordering information part number isl28213fhz 8 ld sot-23 package as coming soon. -replaced figure 24 simulated input noise voltage with following changes: y-axis from ?10 to 100? to ?10,000 to 10? removed (a) ac sims.dat (active) from top of graph curve changed to improve noise performance made changes to spice net list as follows: -changed revision from ?c? to ?d? and added improved noise performance to revision line. -changed in voltage noise ?v_v9 29 0 .00035? to ?v_v9 29 0 0.45? ?r_r21 28 0 800e3 tc=0,0? to ?r_r21 28 0 30? -removed tc=0 in input stage from r_r1 through c_cin2 -removed tc=0 in 1st gain stage from r_r9 through r_r12 -removed tc=0 in 2nd gain stage from r_r13 through c_c3 -changed in common mode gain stage with zero ?g_g5 v++ vc vcm vmid 2.5118e-10? to ?g_g5 v++ vc vcm vmid 0.25118? ?g_g6 v-- vc vcm vmid 2.5118e-10? to ?g_g6 v-- vc vcm vmid 0.25118? removed tc=0 from r_r16 through r_r23 -changed in pole stage ?g_g7 v++ 23 vg vmid 188.49e-6? to ?g_g7 v++ 23 vg vmid 0.18849? ?g_g8 v-- 23 vg vmid 188.49e-6? to ?g_g8 v-- 23 vg vmid 0.18849? removed tc=0 from r_r17 through c_c5 removed tc=0 in output stage with correcti on current sources from r_r19 and r_r20 made changes to spice schema tic figure 21 as follows: -input stage - modified connection to the eos (voltage control voltage source) -added to thermal information 8 ld sot-23 as tbd -added to pin configuration for the isl28213 8 ld sot-23 12/16/09 fn6728.3 removed ?coming soon? from msop packag e options in the ?ordering information? on page 2. updated the theta ja for the msop package option from 170c/w to 180c/w on page 4. 11/17/09 fn6728.2 removed ?coming soon? from sc70 and sot-23 package options in the ?ordering information? on page 2. 11/12/09 fn6728.1 changed theta ja to 250 from 300. added license statement (page 10) and reference in spice model (page 12). 10/26/09 fn6728.0 initial release
isl28113, isl28213, isl28413 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6728.5 june 9, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl28113 , isl28213 , isl28413 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php
isl28113, isl28213, isl28413 17 fn6728.5 june 9, 2011 small outline transistor plastic packages (sc70-5) d e 1 e e1 c l c c l e b c l a2 a a1 c l 0.20 (0.008) m 0.10 (0.004) c c -c- seating plane 4 5 123 view c view c l r1 r 4x 1 4x 1 gauge plane l1 seating l2 c plane c base metal with c1 b1 plating b 0.4mm 0.75mm 0.65mm 2.1mm typical recommended land pattern p5.049 5 lead small outline transistor plastic package symbol inches millimeters notes min max min max a 0.031 0.043 0.80 1.10 - a1 0.000 0.004 0.00 0.10 - a2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 d 0.073 0.085 1.85 2.15 3 e 0.071 0.094 1.80 2.40 - e1 0.045 0.053 1.15 1.35 3 e 0.0256 ref 0.65 ref - e1 0.0512 ref 1.30 ref - l 0.010 0.018 0.26 0.46 4 l1 0.017 ref. 0.420 ref. - l2 0.006 bsc 0.15 bsc 0 o 8 o 0 o 8 o - n5 55 r 0.004 - 0.10 - r1 0.004 0.010 0.15 0.25 rev. 3 7/07 notes: 1. dimensioning and tolerances per asme y14.5m-1994. 2. package conforms to eiaj sc70 and jedec mo-203aa. 3. dimensions d and e1 are exclusiv e of mold flash, protrusions, or gate burrs. 4. footlength l measured at reference to gauge plane. 5. ?n? is the number of terminal positions. 6. these dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. controlling dimension: millime ter. converted inch dimen- sions are for reference only.
isl28113, isl28213, isl28413 18 fn6728.5 june 9, 2011 package outline drawing p5.064a 5 lead small outline transistor plastic package rev 0, 2/10 dimension is exclusive of mold flash, protrusions or gate burrs. this dimension is measured at datum ?h?. package conforms to jedec mo-178aa. foot length is measured at reference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 1.60 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 0.08-0.20 see detail x 1.45 max (0.60) 0-3 c b a d 3 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 5 2 4 5 5 end view plane
isl28113, isl28213, isl28413 19 fn6728.5 june 9, 2011 package outline drawing m8.118a 8 lead mini small outlin e plastic package (msop) rev 0, 9/09 plastic or metal protrusions of 0.15mm max per side are not dimensions ?d? and ?e1? are measured at datum plane ?h?. this replaces existing drawing # mdp0043 msop 8l. plastic interlead protrusions of 0.25mm max per side are not dimensioning and tolerancing conform to jedec mo-187-aa 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view 1 typical recommended land pattern top view side view 2 included. included. gauge plane 33 0.25 c a b b 0.10 c 0.08 c a b a 0.25 0.55 0.15 0.95 bsc 0.18 0.05 1.10 max c h 4.40 3.00 5.80 0.65 3.00.1 4.90.15 1.40 0.40 0.65 bsc pin# 1 id detail "x" 0.33 +0.07/ -0.08 0.10 0.05 3.00.1 1 2 8 0.860.09 seating plane and amse y14.5m-1994.
isl28113, isl28213, isl28413 20 fn6728.5 june 9, 2011 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?
isl28113, isl28213, isl28413 21 fn6728.5 june 9, 2011 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
isl28113, isl28213, isl28413 22 fn6728.5 june 9, 2011 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.

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